General information | |
Type | |
Family | |
Part number | |
Frequency (MHz) | 1500 |
Bus speed (MHz) | 400 |
Package type | Micro-FCPGA |
Architecture / Microarchitecture / Other | |
CPUID | 0F24h |
Core stepping | B0 |
Next stepping | |
Next production stepping | |
Manufacturing technology (micron) | 0.13 |
L2 cache size (KB) | 256 |
Core voltage (V) | 1.3 |
Case temperature (°C) | 100 |
Notes on sSpec SL6FN | |
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Intel Mobile Intel Celeron 1.50 GHz SL6FN | |||||||||
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General information | |
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Vendor: | GenuineIntel |
Processor name (BIOS): | Mobile Intel(R) Celeron(R) CPU 1.50GHz |
Logical processors: | 1 |
Processor type: | Original OEM Processor |
CPUID signature: | F24 |
Family: | 15 (0Fh) |
Model: | 2 (02h) |
Stepping: | 4 (04h) |
TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
Cache: | L1 data | L1 instruction | L2 |
---|---|---|---|
Size: | 8 KB | 12K uops | 256 KB |
Associativity: | 4-way set associative |
8-way set associative |
4-way set associative |
Line size: | 64 bytes | 64 bytes | |
Comments: | sectored cache | sectored cache |
Instruction set extensions | Additional instructions | ||
---|---|---|---|
MMX | CLFLUSH | ||
SSE | CMOV | ||
SSE2 | CMPXCHG8B | ||
FXSAVE/FXRSTORE | |||
SYSENTER/SYSEXIT | |||
Major features | Other features | ||
On-chip Floating Point Unit | 36-bit page-size extensions | ||
Debug store | |||
Debugging extensions | |||
Machine check architecture | |||
Machine check exception | |||
Memory-type range registers | |||
Model-specific registers | |||
Page attribute table | |||
Page global extension | |||
Page-size extensions (4MB pages) | |||
Physical address extensions | |||
Self-snoop | |||
Thermal monitor | |||
Thermal monitor and software controlled clock facilities | |||
Time stamp counter | |||
Virtual 8086-mode enhancements |